Conventional wireless communications systems use bit clock recovery mechanisms to synchronize the data between wireless stations. In most instances the only timing information available is a sequence of transitions indicating the bit boundaries (i.e., the clock period). A Digital Phase Lock Loop (DPLL) is a component used in bit clock recovery mechanisms to make bit clock corrections (i.e., synchronize the locally generated clock) based on a comparison between the received data's timing derived from its transitions and that of a locally generated bit clock. FIG. 1 is a typical timing diagram of received data 10, its corresponding sliced data 20, and a locally generated bit clock 30 in a conventional wireless communications system. As FIG. 1 shows, once the locally generated bit clock is synchronized (locked) to the received data, the optimum data clocking points 60 (i.e. maximum value) of the received data can be used for communications.
If a transition occurs outside a pre-determined transition window 40, the local clock frequency is advanced or retarded by a fraction of the bit period depending on whether the transition was late or early, respectively. If the frequency is not continuously corrected, the local data clock will drift relative to the received data and synchronization will be lost. It is common in present wireless systems for synchronization to be lost due to a slip of half a bit. If the relative frequency difference is clearly understood, it is possible to disable the frequency corrections for a period of time and then enable them again, provided this period does not exceed the time to slip by half a bit. This time period can be approximated by: EQU (1/2)*(1/Frequency Error)
For example, if the frequency error is 7.2 Hz, then the time period would be 69.44 ms.
DPLLs are susceptible to corrupt signals that will interfere with the signal locking process. Signal corruption is caused by jitter, noise, interference, multipath fading, or signal strength variations. Signal corruption causes the bit clock recovery mechanism to fail, causing loss of synchronization between the wireless terminal and the base station. In the case where the data consists of digitized voice samples, loss of synchronization manifests itself as a burst of noise at one or both ends of the communication link, depending on how audio muting has been implemented. In severe multi-path environments, loss of synchronization can occur as often as once per minute, which, depending on the wireless communication protocol, can cause a delay of several seconds before the voice path is restored again.
Over-correction occurs in DPLL circuits that have no means of changing the frequency correction rate. For example, if the maximum frequency correction is 1/32 bit for each bit then the corresponding frequency error is 31250 parts per million (ppm). For a DPLL in which the maximum frequency error is specified as 100 ppm (.+-.50 ppm at each end of the wireless link) the DPLL is clearly prone to over-correct, especially when the input signal is badly corrupted due to the reasons stated above. Existing solutions have used receive signal strength and jitter as a measure of the input signal quality to enable and disable the frequency correction mechanism. By enabling and disabling the bit clock recovery mechanism, extraneous signals will be effectively blanked out during portions of the data frame. However, where the multipath effect is severe enough, this solution has not proved fast enough to prevent the bit clock recovery mechanism from failing and loss of synchronization from occurring. This is because where software is required to take this information and provide the enable/disable control signal to the hardware, it is not necessarily possible to disable the frequency correction mechanism fast enough before the DPLL has reacted to the input signal. Thus over-correction may already have taken place and loss of synchronization will occur.
Accordingly, there exists a need for systems and methods for synchronizing a local bit clock with a received bit clock that are not prone to over-corrections.
There also exists a need for systems and methods for synchronizing a local bit clock with a received bit clock that do not rely on signal quality measurements.
It is thus an object of the present invention to provide systems and methods for synchronizing a local bit clock with a received bit clock that do not rely on signal quality measurements.